The present invention relates generally to electronic circuits used to generate clock signals and in particular to digital phase-locked loops (PLLs).
Phase-Locked Loops (PLLs) are circuits that produce an output clock signal whose phase is locked to the phase of an input reference clock signal. Phase, in the context of a PLL, means a signal's frequency value integrated over time, i.e., the signal's accumulated number of clock pulses. The ratio of the frequency of the output clock signal and the frequency of the reference clock signal can be a positive integer number, in which case the PLL is called an integer-N PLL; or it can be a positive rational number, in which case the PLL is called a fractional-N PLL. Rational numbers are numbers that can be expressed as a ratio of two integers. In the context of this document, a fractional-N number is a positive rational number consisting of an integer part (obtained by rounding down to the nearest integer number) and a fractional part.
A PLL includes a controlled oscillator that produces the output clock signal. An analog PLL usually has a voltage-controlled oscillator (VCO), and a digital PLL may have a digitally-controlled oscillator (DCO). A PLL locks the phase (and as a result, frequency) of the output clock signal to the reference clock signal by measuring the accumulated number of output clock cycles, and adjusting the controlled oscillator frequency when the measured number deviates from a required number, referred to as or obtained from a frequency control word (FCW). The ratio of output clock cycles to reference clock cycles, measured over some duration, is called the PLL's multiplication factor. When a PLL is in lock, its multiplication factor matches its FCW.
Frequency-Locked Loops (FLLs) are circuits that produce an output clock signal whose frequency is locked to the frequency of an input reference clock signal. Compared to a PLL, an FLL lacks the integration or accumulation over time. A PLL's integration may occur anywhere in its loop, for example in feedback circuits, or in feedforward circuits such as a loop filter. Whereas a PLL in lock will lock both frequency and phase ratios in output and reference signals, an FLL may lock only the frequency ratio but not necessarily the phase ratio.
In an integer-N PLL, the frequency resolution of the output clock signal equals the frequency of the reference clock signal, since the output clock frequency equals a positive integer number times the reference clock frequency. Increasing or decreasing the positive integer number by one will result in the output clock frequency increasing or decreasing by one times the reference frequency. A finer output frequency resolution can be achieved by using a lower reference clock frequency. However, in practical PLLs this may increase the jitter.
A fractional-N PLL can have a much better output clock frequency resolution without the need for a low reference clock frequency, as the ratio between the output clock and reference clock frequencies can be a positive rational number. An example of a fractional-N PLL is described in U.S. Pat. No. 8,994,523, entitled Phase-Locked Loop Apparatus and Method by Jenkins. The circuits described there provide potentially very high accuracy and low jitter, but at the expense of some energy. However, there is also a need for fractional-N PLLs that consume very little power, even if they operate with more jitter.
While most PLLs and FLLs have a single feedback loop, and are capable of locking to a single reference clock signal, some PLLs have multiple parallel feedback loops, allowing to lock to one of multiple reference clock signals, not necessarily of the same frequency. The capability to switch between the different reference clock signals without facing a discontinuity in phase and therefore a possibly extended lock-in time is called hitless switching. An example hitless switching PLL is described in U.S. Pat. No. 9,007,105 by Jenkins.
A jitter attenuator is a PLL with the capability to provide an output clock signal whose jitter is substantially lower than jitter in the reference clock signal. A jitter attenuator usually has multiple nested feedback loops. For example, it may have one or more primary feedback loops and one secondary feedback loop. The secondary loop may be locked to a highly stable reference source, such as a crystal oscillator, whereas the primary loop(s) may be locked to one or more unstable or jittery reference sources. The jitter attenuator's average output clock frequency may be locked to the frequency of one of the jittery reference sources, whereas its jitter may be determined by the stable reference source.
In many PLLs, whether used for logic clocking, video clocking, instrumentation, wireless, wired or optical communication, there is a need to lower power usage.
Reference to any prior art in the specification is not, and should not be taken as, an acknowledgment or any form of suggestion that this prior art forms part of the common general knowledge in the USA, China, Australia, or any other jurisdiction or that this prior art could reasonably be expected to be ascertained, understood and regarded as relevant by a person skilled in the art.